1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to an ESD protection circuit, an ESD protection apparatus, and a semiconductor structure adapted for ESD protection.
2. Description of the Related Art
Lately, with the advance of semiconductor technology, the integration of semiconductor devices has been increased by shrinking the line width and increasing the number of deposited film layers. However, while dimensions of integrated circuits shrink, the tolerable currents for circuits are also reduced. As a result, the minimized integrated circuits are more vulnerable to electrostatic discharge (ESD). When ESD is received by circuit devices, a huge voltage or current flows through the circuit devices in a very short time, thereby may burn up or puncture the circuit devices in an instant.
In order to avoid ESD damage, ingeneral an ESD protection circuit is disposed between a high-voltage terminal (VDD) and a low-voltage terminal (VSS) of an integrated circuit to bypass and prevent an ESD current from flowing through the integrated circuit.
FIG. 1A is a schematic drawing showing a conventional ESD protection circuit. Referring to FIG. 1A, the ESD protection circuit 100a comprises a gate-grounded N-type metal-oxide-semiconductor (GGNMOS) transistor 108, which is coupled between two pads 104 and 106 of the integrated circuit 102. Wherein, the pad 104 is coupled to the voltage VDD, and the pad 106 is coupled to the voltage VSS. The drain of the NMOS transistor 108 is coupled to the pad 104, and its source, gate, and substrate terminal are coupled to the pad 106. Accordingly, when ESD voltage is received, the parasitic bipolar transistor 110 of the NMOS transistor 108 turns on the NMOS transistor 108 to bypass the ESD current, as shown in the dotted line 110 in FIG. 1.
FIG. 1B is a schematic drawing showing another conventional ESD protection circuit. Referring to FIG. 1B, the ESD protection circuit 100b is coupled between the two pads 104 and 106 of the integrated circuit 102. The ESD protection circuit 100b comprises the capacitor 112, the resistor 114, and the NMOS transistors 116 and 118. Wherein, the pad 104 is coupled to the voltage VDD, and the pad 106 is coupled to the voltage VSS. The capacitor 112 is coupled between the voltage VDD and the node N1. The resistor 114 is coupled between the voltage VSS and the node N1. The gate of the transistor 116 is coupled to the node N1, its drain is coupled to the voltage VDD, its substrate terminal is coupled to the voltage VSS, and its source is coupled to the substrate terminal of the transistor 118. The gate of the transistor 118 is grounded, its drain is coupled to the voltage VDD, and its source is coupled to the voltage VSS. The transistor 118 also comprises a parasitic bipolar transistor 120 as shown in the dotted line 120 in FIG. 1B.
Referring to FIG. 1B, the resistance-capacitance (RC) constant of the resistor 114 and the capacitor 112 is larger than the rising time of the ESD voltage. When ESD voltage is received, the voltage of the node N1 reaches the voltage VDD swiftly, and turns on the transistor 116. After the transistor 116 is turned on, the source voltage is substantially equal to the drain voltage VDD, so the parasitic bipolar transistor 120 of the transistor 118 turns on the transistor 118 to bypass the ESD current.
FIG. 5 is a schematic drawing showing relationships between currents and voltages of the conventional ESD protection circuit and the ESD protection circuit of the present invention. Referring to FIG. 5, the curve C1 represents the relationship between the currents and voltages of the ESD protection circuit shown in FIG. 1A. Some disadvantages are apparent. For example, when a small ESD voltage is received, no ESD current is bypassed until the ESD voltage reaches a high level. As a result, its turn-on efficiency is not rapid enough, therefore causing puncturing or burning of the ESD protection circuit. Also, the ESD protection circuit may not protect the internal devices of the integrated circuit. In addition, the curve C2 represents the relationship between the currents and voltages of the ESD protection circuit shown in FIG. 1B. Though the disadvantage in the circuit of FIG. 1A is improved, the bypassed ESD current is not sufficient while a small ESD voltage is received. Only after the ESD voltage reaches a high level will the bypassed ESD current slowly become high. Accordingly, the turn-on efficiency of the ESD protection circuit is still not instant. Therefore, a novel ESD protection circuit with high turn-on efficiency is desired.